The present invention generally relates to a method of applying heat treatment to a multilayer semiconductor wafer having a peripheral edge. In particular, selected portions of the peripheral edge are thermally treated to compensate for local differences in heat absorption. This establishes a substantially equivalent temperature over both the surface of the central region and the surface of the peripheral edge to prevent the appearance of slip lines on those surfaces. An application of the invention relates to silicon on insulator (SOI) type wafers that include a working top layer of silicon, an insulating intermediate layer which may be an oxide layer, and a bottom support layer.
The term “multilayer wafer with an edge” is used herein to mean a wafer of semiconductor material which includes the following two characteristics. First, the wafer is a “multilayer” wafer, which means that it is made of an assembly of at least two layers. Second, the multilayer wafer has an “edge”, meaning that it has a peripheral edge (it being understood that the type of wafers to which the invention relates are generally circular in shape) presenting a step in thickness. Typically, at least one upper layer of the wafer is not present in the peripheral edge, and thus only the lower layer(s) is/are present.
Methods suited for obtaining SOI type wafers include transfer methods which create and utilize a zone of weakness. Under such circumstances, a working layer of silicon is obtained from a silicon substrate in which the zone of weakness has been created. For example, a SMART-CUT® type method may be used.
When a SOI wafer is detached from its substrate along the zone of weakness, only the central portion (which, seen from above, is the largest portion of the wafer) of the silicon layer is actually detached from the substrate. Detachment does not actually occur in the peripheral region of the wafer. Thus, the resulting SOI wafers include an “edge” in the form of a downward step. FIG. 1 illustrates such a step in a highly diagrammatic and simplified manner. In particular, FIG. 1 shows a SOI wafer 10 after it has been detached from a substrate. The wafer includes a support layer 100, an insulating layer 101, and a working layer 102 of silicon. The layers 101 and 102 define a peripheral edge 1020 that is a few millimeters wide. Such wafers are generally subjected to heat treatments, which may be for the purpose of modifying the composition of one or more layers of the wafer, or for stabilizing a bonding interface between two layers, or for curing structural defects, and/or for improving the surface state of the wafer, for example. Such heat treatments (or annealing operations) can be implemented in a wide variety of manners. Thus, some annealing operations are performed in temperature ranges that are considered to be “low” for applications of the invention. For purposes of the present specification, “low” temperatures are defined by convention as being less than a value of about 500° C. to 600° C. This definition is given solely for the purposes of the present description, and it should be understood that it does not necessarily correspond to a definition that is universally accepted in the field of the invention. Annealing may also be undertaken at “high” temperatures, which means at values greater than about 500° C.–600° C.
One particular mode of high temperature annealing is known as rapid thermal processing (RTP). In RTP mode, the processing temperature is generally very high (typically about 950° C. or higher), and the annealing time is kept down to a duration of the order of a few minutes. It is known to subject SOI type wafers to rapid thermal annealing (RTA) where the temperature reaches values of about 1100° C. to 1250° C., the total duration of annealing being of the order of only a few tens of seconds. The effect of such annealing is to smooth the surface of a wafer, and it is common to find that the roughness specifications for SOI type wafers must not exceed 5 angstroms (Å) in root mean square (rms) value.
Wafers (in particular SOI wafers) can also be subjected to other types of RTP annealing, for example annealing of the rapid thermal oxidation (RTO) type. Such annealing, which is performed under an oxidizing atmosphere, oxidizes the surface of the wafer. Multilayer semiconductor wafers which have an edge may thus be subjected to various types of annealing techniques.
It has been observed that drawbacks are associated with annealing operations performed on such wafers. More precisely, RTP type annealing operations (including RTA, RTO, and the like.) generate defects known as “slip lines” in wafers. Such slip lines are generated in particular by temperature non-uniformities in three dimensions within an annealing furnace (that is, the temperature is not strictly identical at all points). Slip lines develop in the wafer under the effect of the above-mentioned very high levels of thermal stress. It has also been observed that such slip lines are generally initiated in the peripheral region of the wafer. This phenomenon of slip lines at the periphery of the wafer is particularly severe for multilayer wafers having an edge.
RTP type annealing thus tends to generate slip lines, and this drawback is in particular severe for multilayer semiconductor wafers having an edge. Such heat treatments subject the wafer to very high levels of thermal stress because of the very rapid temperature rises they induce.
It should be understood that this major drawback is more severe when annealing is performed by radiating heat from one or more heat sources. A typical illustration is RTP annealing using infrared lamps that emit heat radiation, with the wafer being placed facing the lamps. The generation of slip lines is less severe when annealing is performed by thermal conduction (as happens in an annealing furnace filled with a heat-conducting gas that surrounds the wafer). For annealing that does not involve RTP mode (i.e. annealing performed at low temperature), this drawback is less severe.
However, wafer deformation can still be observed even with low-temperature annealing. Such deformation is typically associated with wafers bending or twisting to some extent, as can be observed, for example by variation in the warp of the wafer. Warp represents the maximum deformation of the wafer relative to an “ideal” wafer, which is a wafer that is absolutely flat. Such warp can also be observed when annealing is performed in RTP mode. Therefore, there are several drawbacks when annealing is performed on multilayer semiconductor wafers that include an edge.
Certain documents suggest solutions for locally heating a wafer, for example, by selectively powering infrared lamps positioned to face different regions of the wafer. However, the documents do not seek to solve the particular problem mentioned above. Such documents are generally limited to treating simple single-layer wafers without edges, where the specific problem of generating slip-lines on multilayer wafers having an edge does not arise.
Other documents suggest solutions for controlling heating at the periphery of a wafer, by using a thermal continuity ring. However the teaching of those documents is limited to setting up a thermal continuity ring in order to avoid edge effects which do not correspond to the specific problem mentioned above.
Examples of documents relating to the above-mentioned prior art techniques include the following. International Application No. WO 01/69656 discloses a ring which acts in a conventional manner to absorb heat and to return it to the wafer it surrounds, in particular without in any way adapting the ring or its disposition in order to address the specific problem of generating slip lines. Published U.S. Application No. 2001/036219, and U.S. Pat. No. 5,937,142 propose locally heating a wafer which is not a multilayer wafer. U.S. Pat. Nos. 6,235,543 and 6,184,498 propose systems that enable conditions under which defects appear in a wafer to be characterized, wherein the wafer is not a multilayer wafer, and for the purpose of subsequently modifying the heating treatment as a function of those conditions under which defects appear. Lastly, U.S. Pat. Nos. 5,011,794, 6,570,134, 4,958,061, and 6,051,512 describe thermal continuity rings and ways of implementing them.
None of these documents concerns the problem of preventing the appearance of defects such as slip lines that are generated due to a difference of heat-absorption coefficients at the edge of a multilayer semiconductor wafer. Furthermore, none of those documents even mentions problems associated specifically with multilayer wafers.